1. Introduction

After the completion of a long process of the FeFET device structuring, meshing, regioning, calibration and simulation, the simulation data is logged and stored in ”.str” formats (abbreviation for structure files) which is used to save the structural properties of the device at a particular time during simulation, as well as in ”.log” files, which logs data like current, voltage, capacitance, etc. while performing voltage sweeps. These files are saved with the help of trigger code lines in the incode file for the device, which is the main file which contains all the code for the simulation.

Both types of files can be opened and graphically visualised using TonyPlot Software, which offers a variety of tools to graph different characteristics using the data stored in those files. However, the data is not stored in a format that can be directly used in the Verilog-A model, and needs to be manipulated and processed to be used in the model.

This is a tedious process, and can be automated using Python, which can be used to extract the data from the files, process it, and then manipulate it to be used in the Verilog-A model for Simulation in Advance Design System (ADS).

2. Raw Data

As can be seen in the figure above, the log files for FeFET devices amount to a lot as each Drain Voltage (VD) bias generates its own LogFile for each sweep of Gate Voltage (VG) from -1V to 2.6V, with a step up of 0.02V in Drain Voltage for the next (VG) Sweep, till (VD) reaches 2.6V. The same is done for Ramp Down, only in this case, the (VG) Sweep goes in a negative direction from 2.6V to -1V, and the (VD) also goes from 2.6V to -1V with a step size of -0.02V.

This means a total of 362 .log files are generated

This is a tedious process, and can be automated using Python, which can be used to extract the data from the files, process it, and then manipulate it to be used in the Verilog-A model.

The data in each of these exported ”.dat” files needs to be processed in a format using which the data can be formatted and used in our ADS Verilog Table Files .

3. Data Extraction

To extract, process and manipulate this data from these ”.dat” files into a suitable format, we use Python along with libraries like numpy and pandas

The data in ”.dat” files are in a format that is not easy to read in its raw format, thus is not in a usable state. After using pandas to read and extract the data from the ”.dat” file, the data is sorted in a format which is somewhat understandable, as can be seen in the figure above, however this is still not in a format that can be used in the Verilog-A model.

4. Data Processing

After the data of a file is successfully extracted from a ”.dat” file, it is stored temporarily as a Dataframe, which is a utility offered by the Pandas library in Python. However, the dataframe has just stored the data in row and column format, so we process the data to give some definition to the data to be able to manipulate it as per our needs.

Now we have the data sorted out in a understandable format, with the columns marked with the respective values of the:

(CGS) - Capacitance Gate Source

(CSD) - Capacitance Gate Drain

(CGD) - Capacitance Gate Drain

(ID) - Drain Current

for the Gate Voltage (VG) sweep from -1V to 2.6V with a step size of 0.02V giving us a total of 181 rows and 5 column table for each file!

5. Data Manipulation

Since we have each file sorted out in an understandable format, we can now manipulate the data to be used in the Verilog-A model.

Three table files are required by ADS Verilog Table files in order to feed the ADS component the data it required for simulation. These three table files are:

ID Table File

CGS Table File

CGD Table File

Each of these table files requires 2 columns in common, which are VD and VG. The third column contains its characteristics data, meaning ID Table File will have ID as its third column, CGS Table File will have CGS as its third column and CGD Table File will have CGD as its third column

To achieve this, numpy is used to create a completely new column for VD, and pandas is used to strip the required columns from the extracted dataframe, and append the required columns to generate 3 separate dataframes, which can be seen in the figure above

6. Automation

After the three required tables are generated after Data Extraction and Processing, the data is now in a usable state. However, this was performed on just 1 of the 362 ”.dat” files.

Also, all the data generated in form of the three separate table files needs to be consolidated into 3 main table files for ID, CGS and CGD

Performing these steps one by one for each step will be very time-consuming, therefore the code used till now is put into a loop to make an Automated Python Script , which will automatically read all the ”.dat” files one by one, process them, and store the data into 3 main table files for ID, CGS and CGD after segregation of the processed data, and once all the ”.dat” files are covered, extract the table files in ”.csv” format

For Ramp Up and Ramp Down Data (181 Files each), 2 Python scripts were made. For creating data for PMOS FeFET device using the NMOS FeFET data, data manipulation is done, for which 2 more Python scripts were made.

In total, 4 Python Automation Scripts were used for allowing ADS devices to work. As one script generates 3 table files, a total of 12 table files were generated

7. Conclusion

As made evident from the sections above, DEPAM plays an integral part in the process of developing an ADS model for a semiconductor device designed and simulated on Silvaco ATLAS. Without DEPAM, the whole process of making the simulation data usable and ready for ADS Verilog Table files manually would have taken an estimated time of at least a month, assuming that all the work done is error-less.

Using DEPAM, any kind of changes or manipulation deemed necessary for the sake of the experiment can be achieved with just a click, in a neat and orderly manner and can be reliable, as all the repetitive steps are being done by the loops set up in Python script.

No time is spent on searching, opening, copying, pasting, cropping, creating new files, copying the correct data again and pasting the correct data in the desired table files

All these steps are done in less than 12 seconds per script.